1. Field of the Invention
The present invention relates to a timing signal generating circuit for use in various apparatuses.
2. Description of the Prior Art
For example in a floppy disk drive (FDD), one pulse signal is generated every rotation of the disk to decide the start position of recording on the disk rotated by a motor. It is necessary for this signal to be generated at a particular speed of the disk so that the compatibility of the disk is obtained, which is realized by a timing adjustment based on a reference value and the precision of its permissible range.
Referring to FIG. 1, there is shown a conventional timing signal generating circuit. Reference numeral 20 represents a comparator. Reference numeral 21 represents a latch circuit. Reference numeral 22 represent a switching transistor. To an inverting terminal (-) of the comparator 20, a reference voltage V.sub.ref2 is supplied. To a non-inverting terminal (+) thereof, a voltage of a capacitor C is applied.
When a trigger pulse P is inputted to the latch circuit 21 under a condition where the output of the latch circuit 21 is of high level, the output of the latch circuit 21 is inverted to low level as shown in (b) of FIG. 2. Consequently, the transistor 22 is disabled, so that the capacitor C is charged by a current flowing from a line 23 of the reference voltage V.sub.ref1 through a resistor R to increase the voltage across the capacitor C as shown in (c) of FIG. 2. This voltage is inputted to the non-inverting terminal (+) of the comparator 20. When this voltage reaches the reference voltage V.sub.ref2, an output of the comparator 20 becomes of high level. In response thereto, the output of the latch circuit 21 is inverted to high level.
When the output of the latch circuit 21 becomes of high level, the transistor 22 is activated to rapidly discharge the capacitor C, so that the voltage of the capacitor C becomes of low level to change the level of output of the comparator 20 to low level. As a result, the output of the comparator 20 is a narrow pulse as shown in (d) of FIG. 2. The output obtained from an output terminal 24 (in this case, the output of the latch circuit 21) is as shown in (b) of FIG. 2, and the timing period is a period T corresponding to the output pulse width.
In this conventional circuit, however, if the values of the resistor R and the capacitor C vary with temperature variation and with time, the timing period T varies. Specifically, in the conventional circuit, since the timing period T is obtained by ##EQU1## by making V.sub.ref2 /V.sub.ref1 constant, T depends on the values of the capacitor C and the resistor R. In other words, the above expression implies that the timing period T largely varies according to the variation in the values of the capacitor C and the resistor R. For this reason, in the conventional circuit, it is necessary to use as the resistor R and as the capacitor C a resistor and a capacitor which show only extremely slight variation with temperature variation and with time. This is very inconvenient.